1. Field of the Invention
The present invention relates to a nano-wire capacitor and a circuit device employing the capacitor.
2. Description of the Related Art
Recently, with progress of fine working techniques for LSI, improvement of CPU calculation speed, increase of semiconductor memory capacity, and miniaturization of electric devices are progressing remarkably rapidly. However, the patterning of the LSI is conducted by a top-down method including light exposure, the working accuracy thereof being limited to several tens of nanometers. Although scanning tunnel microscopy (STM) and atomic force microscopy (AFM) are useful for forming a several-nanometer structure, the techniques are not readily applicable to a larger-area structure. Therefore, a novel technique is necessary for higher integration of electronic circuits.
For solving the above problem, one method disclosed is use of nano-wires for the electronic circuit formation. The nano-wire is produced mainly by the bottom-up method. Therefore, the nano-wire is expected to provide a circuit at a density higher by one or more digits than that of conventional circuits provided by the top-down method. Since the size of several nano-meters is expected to give a novel effect like the quantum effect, the nano-wire has a possibility of providing, for example, a revolutionary novel device such as a super-high speed switching element utilizing the nonlinear optical characteristics of the quantum effect. Herein, the term “top-down method” is a general term for fine-processing techniques of processing a bulky material to make a product of smaller size. The term “bottom-up method” means a fine-assembling method in which such a smaller substance as the nano-wire is generated and then enlarged.
The nano-wire research includes an FET technique employing a semiconductor nano-wire. The semiconductor nano-wire FET (Field-Effect Transistor) employs a semiconductor nano-wire having high mobility of several-hundred to several-thousand cm2/Vs as the conduction channel, and is promising for finer circuits (e.g., U. S. Patent Application Publication No. 2004/0112964).
The above-mentioned semiconductor nano-wire FET can be formed by applying a dispersion of the semiconductor nano-wires in a solution to a substrate (e.g., X. Duan et al., Nature, 425 (2003) 274). This technique enables formation of a TFT (thin film transistor) of high performance in a large area at a low cost on a desired substrate. Further, the semiconductor nano-wire FET can be formed on a plastic substrate to provide a flexible high-performance TFT, which is applicable as RF-ID (radio frequency identification), a flexible display, a sheet computer, and so forth.
U.S. Patent Application Publication No. 2004/0112964 discloses an FET which employs a nano-wire constituted of semiconductor nano-wire 100 covered with dielectric layer 101 and gate electrode 102, as shown in FIG. 20. By use of the nano-wire having the above constitution in an FET, the gate electrode need not be provided additionally and the drop of the threshold level by overlapping of the nano-wires is prevented. Thereby, a semiconductor nano-wire transistor of high performance is provided through a simple process in comparison with those having a separate gate electrode.